Japan Institute of Physics and Chemistry RIKEN, Fujitsu and NVIDIA jointly announced that they will cooperate to develop the FugakuNEXT super computer. This is the successor of Fugaku, currently ranked seventh in the world, with a budget of 11 billion yen (about 750 million US dollars) and the plan will be put into operation in 2030 at the RIKEN, a Japanese Institute of Physics and Chemistry Research Institute.

This cooperation between the three units and enterprises is the first time that Japan has adopted GPU as core computing in supercomputers in history. Among them, Fujitsu has cooperated with RIKEN, the Japanese Institute of Physics and Chemistry. Fujitsu will lead the basic design of the entire system, computing nodes and CPU, while NVIDIA will lead the design of GPU-based facilities, and the three parties will jointly establish an AI-HPC platform.

FugakuNEXT Super Computer aims to maintain Fugaku's same 40MW power and improve overall performance by 100 times. It not only provides the simulation performance pursued by supercomputers in the past, but also provides the world's leading simulation and artificial intelligence capabilities. After the two are closely combined, a unified AI-HPC platform is further formed. FugakuNEXT will develop three main aspects: FP64 computing power and memory bandwidth, software algorithms, and FP16/FP8 computing power suitable for AI to achieve a significant performance improvement. Among them, the computing power of FP64 will exceed 2.6 ExaFLOP, and the overall memory frequency width will be increased from Fugaku's 163 PB/s to above 800 PB/s. Finally, the AI ​​computing power has been greatly increased from 2 ExaFLOP to above 600 ExaFLOP, which also allows the algorithm to improve by up to 20 times.

In addition, MONAKA will replace the A64FX chip used by Fugaku, which has the core based on the Armv9-A instruction set architecture, supports the SVE2 instruction set, and provides a variable-length vector register. It uses a small chip design, uses CoWoS system-level packaging (SiP) and Broadcom’s first 3.5D F2F packaging technology, with 4 computing modules, each with 36 enhanced Armv9 cores, and will also be manufactured using telco 2nm process technology, and stacked on SRAM modules made with 5nm process technology using hybrid copper bonds (HCB) in Face2Face (F2F). Compatible with computing and storage memory stacking is an I/O module made by 5-nanometer process technology that integrates memory controllers and supports CXL 3.0 and PCIe 6.0 standard connection channels, etc.